Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs

In this paper we have addressed the test infrastructure design for TSV based 3D stacked IC (3D SIC). Each of the die consisting of one or more hard SOCs. Main objective of this work is to design the test architecture for the 3D SIC so that overall test time can be optimized. To prove the efficiency of our proposed algorithm we have considered a 3D stacked IC (SIC) using 5 standard SOCs. Obtained test results show that our proposed solution can achieve up to 59 % reduction in test time compared to the baseline method of sequentially testing all the dies in the stack. We have also shown that increasing the number of test access mechanism (TAM) and through silicon vias (TSVs) help in the reduction of test time but the increase in the number of TAM is unnecessary after a certain limit. In this work we have assumed that the different dies in different layers may consist of two SOCs as opposed to previous work, where each die consists of single SOC.