Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology

Ultra low power-efficient VLSI circuits design received wide attention due to rapid growth of portable applications. The portable domain places inflexible constraint on the power consumption. Though, device operating in sub threshold region shows huge potential towards satisfying the ULP requirement, it holds lots of difficult design issues. As integration density of interconnects increases at every technology node, increased delay and cross talk effects may becomes a more challenging design problem particularly for sub threshold interconnects. Nanometer sub threshold global interconnect faces sub threshold driver design challenges and problems due to increased interconnect capacitance. This paper examined and compared the effect of cross talk on delay for mixed wall carbon nano tube and Cu interconnects. This work reports new aspect ratio for global interconnect to reduce the effect of cross talk on interconnect performance under sub threshold conditions.