DocumentCode
2845821
Title
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
Author
Litz, Heiner ; Froening, Holger ; Nuessle, Mondrian ; Bruening, Ulrich
Author_Institution
Comput. Archit. Group, Univ. of Heidelberg, Heidelberg
fYear
2008
fDate
9-12 Sept. 2008
Firstpage
238
Lastpage
245
Abstract
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a field-programmable-gate-array (FPGA) based prototype we show a latency of 970 ns between two machines with our virtualized engine for low overhead (VELO). The FPGA device is directly connected to the CPUs by a hypertransport link. The described hardware architecture is optimized for small messages and avoids the overhead typically found with direct-memory access (DMA) controlled transfers. The stateless approach allows to use the hardware unit directly from many threads and processes simultaneously. It provides a secure user level communication with an extremely optimized start-up phase. Micro benchmarks results are reported both based on proprietary API and OpenMPI basis.
Keywords
field programmable gate arrays; file organisation; message passing; FPGA; VELO; direct-memory access; field-programmable-gate-array; hypertransport link; submicrosecond latency; ultra-low latency message transfers; virtualized communication engine; Access protocols; Bandwidth; Clocks; Communication system control; Control systems; Delay; Engines; Field programmable gate arrays; Hardware; Parallel processing; fine-grain communication; hpc; low-latency message passing; virtualization;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 2008. ICPP '08. 37th International Conference on
Conference_Location
Portland, OR
ISSN
0190-3918
Print_ISBN
978-0-7695-3374-2
Electronic_ISBN
0190-3918
Type
conf
DOI
10.1109/ICPP.2008.85
Filename
4625855
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