DocumentCode :
2846257
Title :
Understanding scheduling replay schemes
Author :
Kim, Ilhyun ; Lipasti, Mikko H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear :
2004
fDate :
14-18 Feb. 2004
Firstpage :
198
Lastpage :
209
Abstract :
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, scheduling misses should be recovered across the multiple levels of dependence chains in order to prevent further unnecessary execution. We explore the design space of various scheduling replay schemes that prevent the propagation of scheduling misses, and find that current and proposed replay schemes do not scale well and require instructions to execute in correct data dependence order, since they track dependences among instructions within the instruction window as a part of the scheduling or execution process. We propose token-based selective replay that moves the dependence information propagation loop out of the scheduler, enabling lower complexity in the scheduling logic and support for data-speculation techniques at the expense of marginal IPC degradation compared to an ideal selective replay scheme.
Keywords :
instruction sets; parallel architectures; parallel programming; pipeline processing; processor scheduling; IPC degradation; clock cycle; data-speculation technique; dependence information propagation loop; instruction window; microprocessor; scheduling delay; scheduling logic; scheduling replay scheme; speculative scheduling; token-based selective replay; Broadcasting; Clocks; Computer architecture; Dynamic scheduling; Hazards; Joining processes; Processor scheduling; Propagation delay; Radio frequency; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software, IEE Proceedings-
ISSN :
1530-0897
Print_ISBN :
0-7695-2053-7
Type :
conf
DOI :
10.1109/HPCA.2004.10011
Filename :
1410077
Link To Document :
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