Analog VLSI design of multi-phase voltage doublers with frequency regulation

This paper proposes a new organization of charge pump circuits based on a voltage doubler that takes a DC input and outputs a doubled DC voltage. By cascading n multi-phase voltage doublers (MPVD), the resulting charge pump has the voltage gain equal to 2ⁿ. It needs n clock pairs to control the pumping process, MPVD is a minimum capacitance realization of the switched-capacitor based voltage doubler. An n-stage MPVD needs n+1 capacitors and 2ⁿ switches. To avoid the short circuit during switching, a dock pairs generator is used to achieve multi-phase non-overlapping clock pairs. A frequency regulator is designed to lower the charging frequency when the load becomes lighter, thus reducing the power loss during switching. A 2-stage MPVD is implemented in the Orbit 2.0 μm analog CMOS technology. The simulation results show that the output voltage is 3.995 times the power supply. By using the frequency regulator, the power efficiency is dramatically improved when the load becomes lighter