An approach for self-timed synchronous CMOS circuit design

In this paper we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modify the circuit clock period. This paper is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder