DocumentCode
2847377
Title
OpenDSP in Xilinx FPGA
Author
Salim, A.J. ; Otham, M. ; Ali, M. A Mohd
Author_Institution
Pusat Rekabentuk VLSI, Univ. Kebangsaan Malaysia, Selangor, Malaysia
fYear
2005
fDate
5-7 Sept. 2005
Firstpage
185
Lastpage
189
Abstract
This paper describes the implementation of a 16-bit fixed-point DSP chip using the Xilinx Virtex-II FPGA. The design uses the modified IP core (OpenDSP) integrated with RAM and ROM in one FPGA chip. The chip is designed for small general-purpose applications. In order to verify the functionality of the chip, the FFT and IFFT algorithms were developed, implemented and tested to successfully work at a typical clock speed of 40 MHz and up to a maximum of 80 MHz.
Keywords
digital signal processing chips; fast Fourier transforms; field programmable gate arrays; industrial property; random-access storage; read-only storage; 40 MHz; 80 MHz; OpenDSP; RAM; ROM; Xilinx Virtex-II FPGA; fixed-point DSP chip; Application software; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Hardware design languages; Mathematical model; Microcontrollers; Read only memory; Signal processing algorithms; Testing; FPGA; ModelSim; OpenDSP; Spreadsheet and Matlab; Verilog; Visual Basic; Xilinx;
fLanguage
English
Publisher
ieee
Conference_Titel
Sensors and the International Conference on new Techniques in Pharmaceutical and Biomedical Research, 2005 Asian Conference on
Print_ISBN
0-7803-9370-8
Type
conf
DOI
10.1109/ASENSE.2005.1564536
Filename
1564536
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