Implementation and Design of CPLD-Based Switched-Capacitor Step-Down DC-DC Converter with Multiple Output Choice

A simple quasi-switched-capacitor (QSC) step-down DC-DC converter with multiple output choice (9 V/5 V, 9 V/3.3 V, 9 V/2 V) is designed and implemented via complex-programmable-logic-device-based (CPLD) digital controller for low-power applications (input: 7.0-9.0 V, load: 50~400 Ohms). The integrated digital controller is implemented by combination with verilog CPLD and ADC/DAC chips to achieve the closed-loop control of QSC converter. Such a Verilog-based CPLD can make controller design more flexible, simple and reliable. In fact, SC circuit needs no inductive element, so I.C. fabrication is promising, and it is pretty suitable for low-power VLSI applications. An interleaved current-mode control is employed here from battery source interleaved charging to the series capacitors of different cells by a voltage-controlled current source, so the continuous input current comes into being, and it results in a good feature: low electromagnetic interference (EMI). Such a current-mode control is able to not only enhance output robustness against source variation/noise, but also keep regulation capability of converter with loading variation. Finally, the hardware experiments are illustrated to show the efficacy of the scheme designed, where some topics include: voltage conversion and output ripple percentage, output robustness against source variation, and regulation capability of converter with loading variation.