DocumentCode
2847509
Title
Topological layout design of monolithic IC in computer-aided design
Author
Yoshida, K. ; Nakagawa, T.
Author_Institution
Tokyo Shibaura Electric Co., Ltd., Kawasaki, Japan
Volume
XII
fYear
1969
fDate
19-21 Feb. 1969
Firstpage
136
Lastpage
137
Abstract
This paper will discuss a topological layout project for IC components using a computer, based on given circuit diagrams and order of bonding pads.
Keywords
Capacitors; Conductors; Design automation; Diodes; Integrated circuit layout; Monolithic integrated circuits; Page description languages; Resistors; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1969.1154697
Filename
1154697
Link To Document