An LLC-OCV Methodology for Statistic Timing Analysis

Author

Hong, Jerry ; Huang, Kevin ; Pong, Peter ; Pan, J.D. ; Kang, Jiawen ; Wu, K.C.

Author_Institution

Faraday Technol. Corp., Hsinchu

fYear

2007

fDate

25-27 April 2007

Firstpage

1

Lastpage

4

Abstract

With further increase in chip size and shrink in device dimension, the influence of on chip semiconductor process variation can no longer be ignored in design phase such as STA sign-off. This paper presents the LLC-OCV methodology, which adopts the Monte Carlo analysis to enhance the location-based OCV (LOCV) with gate-level and cell-based perspectives, to be used as a reasonable and complete intra-die process model for STA (statistic timing analysis) sign-off. This new approach shows good prediction for STA sign-off. With LLC-OCV methodology, this paper has correctly identified timing problems in real silicon projects of 0.13 mum process in STA sign-off stage. Comparing the STA results of LOCV and LLC-OCV methodology, our experiment shows that LLC-OCV approach can avoid pessimistic analysis and save chip area.

Keywords

Monte Carlo methods; integrated circuit modelling; semiconductor process modelling; statistical analysis; LLC-OCV methodology; Monte Carlo analysis; chip size; device dimension; intra-die process model; location level cell-based on chip variation methodology; location-based on chip variation; on chip semiconductor process variation; size 0.13 mum; statistic timing analysis; Circuit optimization; Cities and towns; Design for manufacture; Fluctuations; Manufacturing processes; Monte Carlo methods; Semiconductor device measurement; Silicon; Statistical analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0583-1

Electronic_ISBN

1-4244-0583-1

Type

conf

DOI

10.1109/VDAT.2007.373199

Filename

4239391