A Low-Power Low-Swing Single-Ended Multi-Port SRAM

Author

Yang, Hao-I ; Chang, Ming-Hung ; Lai, Ssu-Yun ; Wang, Hsiang-Fei ; Hwang, Wei

Author_Institution

Nat. Chiao-Tung Univ., Hsinchu

fYear

2007

fDate

25-27 April 2007

Firstpage

1

Lastpage

4

Abstract

In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64times32-bit SRAM macro is simulated in TSMC 130 nm CMOS technology. It consumes a minimum of 725 muW and 658 muW per-port at 1 GHz with 1.2 V supply voltage for read and write power, respectively.

Keywords

CMOS digital integrated circuits; SRAM chips; 1-T equalizer insertion; CMOS technology; PVT-tolerance ability; floating virtual ground; frequency 1 GHz; low-power multi-port SRAM; low-swing single-ended multi-port SRAM; low-swing writing ability; noise-rejection; power 658 muW; power 725 muW; single-ended current-mode sensing amplifier; size 130 nm; static noise margin; voltage 1.2 V; CMOS technology; Energy consumption; Engines; Equalizers; Information systems; Microelectronics; Random access memory; Signal design; Voltage; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0583-1

Electronic_ISBN

1-4244-0583-1

Type

conf

DOI

10.1109/VDAT.2007.373203

Filename

4239395