Title :
Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability
Author :
Ker, Ming-Dou ; Hu, Fang-Ling
Author_Institution :
Nat. Chiao-Tung Univ., Hsinchu
Abstract :
A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2timesVDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-mum CMOS process to receive 3.3-V (2timesVDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.
Keywords :
CMOS integrated circuits; buffer circuits; hot carriers; integrated circuit design; integrated circuit reliability; CMOS process; hot-carrier reliability; hot-carrier-prevented circuits; mixed-voltage I/O buffers; size 0.18 mum; Atherosclerosis; CMOS process; CMOS technology; Circuit synthesis; Degradation; Hot carriers; Laboratories; Nanoelectronics; Signal processing; Voltage;
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
DOI :
10.1109/VDAT.2007.373205
