Maximizing Full-Chip Simulation Signal Visibility for Efficient Debug

The most expensive parts of today\´s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort. Unfortunately, far too much time and money are wasted on tasks that don\´t add value -such as trying to figure out how supposedly-correct IP is actually working, debugging "dumb" errors, or deciding what signals to record in any given simulation run. With small block-level simulation, it is practical to record every value change on every signal. This produces a rich database of time-ordered event data that can be used for understanding the block\´s behavior and debugging errors. However, for large subsystem or full-chip level simulation, the overhead required to record all the events on all the signals overwhelms the run-time and fills the available disk space. Run times can explode by a factor of five. Disk requirements can run to the 100 s of gigabytes. The emergence of visibility enhancement technologies enables engineers to make intelligent tradeoffs between impact (simulation performance and file size) and visibility.