Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System

This paper presents a new scheme that reduces the modeling efforts of a transactor while retaining the performance of transaction-based verification for hardware/software co-emulation system. The conventional transaction-based verification requires the designer to develop a synthesizable transactor which interfaces with unfamiliar emulation-system-dependent protocol. The proposed method locates the transactor in the software side instead of in the hardware emulator. This allows easy-to-develop transactor described in high-level language. To reduce the communication time between testbench and DUT, we make the signal flow uni-directional by exploiting existing HDL testbench. The experimental results show that the proposed method is applicable to real-world test environment.