Title :
Topological synthesis procedure for circuit integration
Author :
Engl, W. ; Mlynski, D.
Author_Institution :
Technische Hochschule Aachen, Aachen, Germany
Abstract :
A computer-aided topological layout of components and wiring in integrated circuits will presented based on a new kind of graph which accounts for all technological restrictions, as well as possibilities.
Keywords :
Bonding; Circuit synthesis; Integrated circuit layout; Integrated circuit synthesis; Iterative algorithms; Leg; Packaging; Resistors; Silicon compounds; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1969.1154721
