Title :
Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs
Author :
Yu, Jiunn-Der ; Li, Jin-Fu ; Tseng, Tsu-Wei
Author_Institution :
Nat. Central Univ., Jhongli
Abstract :
Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.
Keywords :
built-in self test; crosstalk; embedded systems; integrated circuit testing; random-access storage; BIST design; TSMC; address buses; crosstalk faults testing; data buses; embedded RAM; parallel wires; random access memories; size 0.18 mum; standard cell library; Built-in self-test; Capacitance; Circuit faults; Crosstalk; Data buses; Delay; Fault detection; Integrated circuit interconnections; Read-write memory; Testing;
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
DOI :
10.1109/VDAT.2007.373218
