DocumentCode :
2847965
Title :
A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm
Author :
Wang, Qi ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi
Author_Institution :
Production & Syst. Waseda Univ., Kitakyushu
fYear :
2007
fDate :
25-27 April 2007
Firstpage :
1
Lastpage :
4
Abstract :
In this paper we proposed a fully-parallel irregular LDPC decoder which uses only registers to store the temporary intrinsic messages. Our decoder adopts a simplified min-sum algorithm to reduce the hardware implementation complexity and area, and due to the factor modification we achieve a negligible performance loss compared with the general min-sum algorithm. Considering reducing the power consumption, we also propose a power-saved strategy according to which the message evolution will halt as the parity-check condition is satisfied. This strategy will save us higher than 50% power under good channel condition. The synthesis result in 0.18 mum CMOS technology shows our decoder for (648,540) irregular LDPC code achieves high throughput (1 Gbps) with 9.0 ns latency.
Keywords :
CMOS digital integrated circuits; decoding; low-power electronics; parity check codes; CMOS technology; intrinsic message storage; min-sum algorithm; parity-check condition; power-saved irregular LDPC decoder; registers; size 0.18 micron; Algorithm design and analysis; CMOS technology; Delay; Energy consumption; Hardware; Iterative decoding; Parity check codes; Performance loss; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
Type :
conf
DOI :
10.1109/VDAT.2007.373219
Filename :
4239411
Link To Document :
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