A Low-Power Viterbi Decoder Based on Scarce State Transition and Variable Truncation Length

Author

Lin, Dah-Jia ; Lin, Chien-Ching ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi

Author_Institution

Nat. Chiao Tung Univ., Hsinchu

fYear

2007

fDate

25-27 April 2007

Firstpage

1

Lastpage

4

Abstract

The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

Keywords

OFDM modulation; VLSI; Viterbi decoding; convolutional codes; low-power electronics; ultra wideband communication; MB-OFDM UWB applications; SNR; convolutional codes; low power mechanisms; low-power Viterbi decoder; scarce state transition; scarce state transition technique; survivor memory; variable truncation length; Convolutional codes; Decoding; Energy consumption; Information retrieval; Merging; Power engineering and energy; Power engineering computing; Registers; Switches; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0583-1

Electronic_ISBN

1-4244-0583-1

Type

conf

DOI

10.1109/VDAT.2007.373220

Filename

4239412