DocumentCode :
2848045
Title :
Interleaving of Gate Sizing and Constructive Placement for Predictable Performance
Author :
Kim, Sungjae ; Shragowitz, Eugene ; Karypis, George ; Lin, Rung-Bin
Author_Institution :
Univ. of Minnesota, Minneapolis
fYear :
2007
fDate :
25-27 April 2007
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.
Keywords :
integrated circuit layout; constructive placement; fast fixed-die standard cell placement algorithm; gate sizing; net delay bounds; placement construction process; row-by-row construction; timing constraints; top-down partitioning; Algorithm design and analysis; Computer science; Delay effects; Energy consumption; Finishing; Interleaved codes; Partitioning algorithms; Routing; Switching circuits; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
Type :
conf
DOI :
10.1109/VDAT.2007.373225
Filename :
4239417
Link To Document :
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