DocumentCode
2848084
Title
A Low-Complexity Fractional Delay All-Pass Filter Design for Time-Domain Interpolation
Author
Wang, To-Ping ; Chiueh, Tzi-Dar
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
fDate
25-27 April 2007
Firstpage
1
Lastpage
4
Abstract
Fractional delay (FD) filter is widely used in digital receiver for time-domain interpolation, such as for compensating sampling clock offset (SCO). Thiran IIR filter is an FD all-pass filter that can retain excellent frequency response. This paper presents an low-complexity implementation of the Thiran filter with application to the sampling clock offset compensation block in digital communication receivers.
Keywords
IIR filters; all-pass filters; frequency response; interpolation; receivers; time-domain analysis; Thiran IIR filter; digital communication receivers; digital receiver; frequency response; low-complexity fractional delay all-pass filter; sampling clock offset; time-domain interpolation; Clocks; Delay; Digital filters; Feedforward systems; Frequency; Hardware; IIR filters; Interpolation; Sampling methods; Time domain analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0583-1
Electronic_ISBN
1-4244-0583-1
Type
conf
DOI
10.1109/VDAT.2007.373227
Filename
4239419
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