DocumentCode
2848266
Title
A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding
Author
Liu, Po-Sheng ; Chen, Jian-Wen ; Lin, Youn-Long
Author_Institution
Nat. Tsing Hua Univ. Hsin-Chu, Hsinchu
fYear
2007
fDate
25-27 April 2007
Firstpage
1
Lastpage
4
Abstract
We propose a full hardwired context-based adaptive binary arithmetic encoder for H.264/AVC. Our architecture includes a 14-way context pair generator, a 3-stage pipelined circuit for getting neighboring data and a 4-stage pipelined multiple-mode arithmetic encoder. The context pair generator is composed of binarization and context modeling and it can operate with arithmetic encoder concurrently. The arithmetic encoder can process one bin per cycle. Our whole CABAC encoder is able to process 0.67 bins per cycle on the average. Its performance is adequate for 1080 p (HDTV) resolution at 30 fps when running at 60 MHz.
Keywords
adaptive codes; arithmetic codes; binary codes; codecs; high definition television; video coding; 14-way context pair generator; 3-stage pipelined circuit; 4-stage pipelined multiple-mode arithmetic encoder; CABAC encoder; H.264 advanced video coding; H.264/AVC; HDTV; binarization; context modeling; frequency 60 MHz; hardwired context-based adaptive binary arithmetic encoder H.264 advanced video coding; Automatic voltage control; Computer science; Context modeling; Digital arithmetic; Encoding; Engines; Entropy; IEC standards; ISO standards; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0583-1
Electronic_ISBN
1-4244-0583-1
Type
conf
DOI
10.1109/VDAT.2007.373239
Filename
4239431
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