Title :
A 40-NS, 144-bit N-channel MOS-IC memory
Author :
Yamamoto, Hiroshi ; Shiraishi, Masashi ; Kurosawa, T.
Author_Institution :
Nippon Electric Co., Ltd., Tokyo, Japan
Abstract :
A monolithic MOS 144-bit random access memory has been fabricated, using N-channel MOS transistors. The memory operates with a 10-ns access time, 30-ns non-destructive read cycle time, and a 40-ns write cycle time.
Keywords :
Assembly; Capacitance; Circuits; Large scale integration; MOSFETs; Packaging; Read-write memory; Substrates; Variable structure systems; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1969.1154744
