DocumentCode
2848308
Title
A high-performance monolithic store
Author
Ayling, J. ; Moore, R. ; Tu, Guojie
Author_Institution
IBM Corp., Poughkeepsie, NY, USA
Volume
XII
fYear
1969
fDate
19-21 Feb. 1969
Firstpage
36
Lastpage
37
Abstract
A 40-ns access bipolar monolithic memory of 2021 words × 144 bits capacity has been developed and incorporated in a computing system. The design and structure of a 64-bit silicon chip will be presented and some aspects of the organization and circuit design discussed.
Keywords
Capacitance; Circuits; Decoding; Delay; Impedance; Logic; Resistors; Signal design; Switches; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1969.1154746
Filename
1154746
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