Title :
Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver
Author :
Tseng, Chi-Yao ; Wei, Ting-Chen ; Liu, Wei-Chang ; Jou, Shyh-Jye
Author_Institution :
Nat. Central Univ., Jhongli
Abstract :
From hardware point of view, system and RTL low power and power aware design techniques are applied to the DVB-T/H baseband inner receiver. In RTL design, we use pre-computation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture so that each block can reduce power from 3% to 26%. In system level, the proposed DPM (dynamic power manager) is a power control unit for our system. When the system enters the offset tracking mode, the DPM controls the power states of system blocks between the GI (guard interval) period and symbol period. The power reduction ratio ranges from 3%~20% (it depends on the Gl mode). Moreover, a predicted phase scheme is proposed to provide the initial phase offset for the start of symbol period during offset tracking mode. The overall reduction for synchronization loop is about 50% in both hardware area and power.
Keywords :
digital video broadcasting; encoding; low-power electronics; television receivers; DVB-T/H baseband inner receiver; RTL design; differential encoding; digital video broadcasting; dynamic power manager; hardware sharing; low power arithmetic architecture; low power design; power aware design; power control unit; time-multiplexing R/W; Baseband; Control systems; Digital video broadcasting; Energy management; Frequency synchronization; Hardware; OFDM modulation; Power system management; TV broadcasting; Telecommunication standards;
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
DOI :
10.1109/VDAT.2007.373245