Systematic development of architectures for multidimensional DSP using the residue number system

A systematic methodology for mapping multidimensional algorithms onto array processor architectures based on the quadratic residue number system is presented. A class of algorithms with separable functions, which can be reduced to the computation of the circular convolution is considered. The array architecture results systematically from a directed graph using partitioning techniques and consists of identical processing elements called inner product step processors. Moreover, due to various graph partitions, many alternative array architectures in terms of I/O constraints, throughput, and hardware complexity can be derived