A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter

A digital background calibration for time-interleaved ADC is presented. By using LMS-FIR and interpolation filter, mismatches of offset, gain, bandwidth, and sample-time error are calibrated. Adaptively controlled by correlation evaluation, the calibration is applicable for most input cases. A 14-bit 200-MS/s two-channel time-interleaved ADC is prototyped in a 0.18-µm CMOS process with core area of 15.2 mm². The ADC achieves an SFDR of 88.9 dBc and an SNDR of 69.5 dBc after calibration, consuming 460 mW at 1.8 V.