The lithography with low-COO and high-performance for advanced packaging

Lithography technology for advanced packaging is quite different from that for other applications. Because the applications of WLP and wafer bumping often require lithography system to define bumping-array patterns across the wafer or to create redistribution a layers or integrated passive devices with resist lagers of thick (20-100μm) and feature sizes large (2-150μm). At the same time, the package process is extremely cost-sensitive and requires nearly perfect yield with very thick photoresist and photopolymer layers as presented in J. Hermanowski (2004). In this paper, we would like to introduce a lithography system with low-COO and high performance, it can meet and allow the requirements of advanced packaging.