A Novel P-Poly Gate PNOS Device Featuring High 2nd-Bit Operation Window for Multi-bit/cell Flash Memory Applications

Author

Wu, Jau-Yi ; Kuo, Ming-Chang ; Yu, Chao-Lun ; Hsu, Tzu-Hsuan ; Lee, Ming-Hsiu ; Hsieh, Kuang-Yeu ; Liu, Rich ; Lu, Chih-Yuan

Author_Institution

Macronix Int. Co. Ltd., Hsinchu

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

2

Abstract

A novel PNOS (P-poly Nitride-Oxide-Si) device that exploits gate edge assisted hole injection is proposed to reduce the 2^nd-bit effect. The device is erased by gate hole injection and programmed by the usual CHE (channel hot electron). Holes are injected from the gate edge using +FN and trapped in the SiN that produce local negative Vt along the channel edge. This edge device in turn causes enhanced DIBL that helps to provide a large 2^nd-bit window (> 4.5 V) that is suitable for MLC operation. Using this device, 4-bit/cell and 6-bit/cell operations are illustrated.

Keywords

MOS integrated circuits; flash memories; 4-bit/cell operation; 6-bit/cell operation; CHE; P-poly gate PNOS device; channel hot electron; flash memory applications; hole injection; Channel hot electron injection; Chaos; Charge carrier processes; Degradation; Electron traps; Flash memory; Silicon compounds; Tellurium; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378902

Filename

4239470