Analysis and architecture design of block matching in BM3D image denoising

Author

Chen, Hongming ; Liu, Wenjiang ; Liu, Taizhi ; Cheng, Yuhua

Author_Institution

Shanghai Res. Inst. of Microelectron. (SHRIME), Peking Univ., Shanghai, China

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

In this paper, a low-cost VLSI implementation for Block Matching (BM) in BM3D image denoising with novel architectures of the slip window and SSD tree are presented. The experimental results show that the proposed technique preserves the BM3D denoising performance and obtains excellent performances in terms of less logic gate count and better visual quality. The design requires only low computational complexity and less SRAM for slip window. Its hardware cost is quite low, about 350k gates. Synthesis results show that the proposed design at a throughput about 177MB/s by using UMC 0.18um technology.

Keywords

SRAM chips; VLSI; computational complexity; image denoising; image matching; logic design; logic gates; BM3D image denoising; SRAM; SSD tree; UMC; architecture design; block matching; computational complexity; hardware cost; image matching; logic gate count; low cost VLSI implementation; slip window; visual quality; Correlation; Image denoising; Noise reduction; Pipelines; Random access memory; Three dimensional displays; Throughput; BM3D; Image denoising; SSD tree; pipeline stage; slip window;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117574

Filename

6117574