Design of back telemetry system on CMOS ON SEMI C5 mixed-signal technology

Author

Rey, J.M.G. ; Ariza, L.F. ; Rozo, A.G. ; Segura-Quijano, F.

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. de los Andes, Bogota, Colombia

fYear

2012

fDate

1-2 Nov. 2012

Firstpage

1

Lastpage

5

Abstract

This paper presents design of a back telemetry system on CMOS ON - SEMI C5 mixed-signal technology. The designed system uses a different schema in order to improve the amount of information sent from the internal unit to the external unit using an alternative scheme without a load modulation strategy. The presented topology has a nontraditional architecture based on a 915 MHz voltage-controlled oscillator LC Cross-Coupled Differential. The designed system has a power consumption of 31.98mW and it represents a 6.5% of total area of 1.5 mm × 1.5 mm chip. The system was validated and simulated through Mentor Graphics IC Nanometer Electronic design automation (EDA) toolkit.

Keywords

CMOS integrated circuits; integrated circuit design; mixed analogue-digital integrated circuits; telemetry; voltage-controlled oscillators; CMOS ON SEMI C5 mixed-signal technology; EDA toolkit; LC cross-coupled differential; Mentor Graphics IC Nanometer Electronic design automation toolkit; back telemetry system design; external unit; frequency 915 MHz; internal unit; load modulation strategy; nontraditional architecture; power 31.98 mW; voltage-controlled oscillator; Coils; Layout; Manganese; Telemetry; Transistors; Voltage-controlled oscillators; Back Telemetry; VCO cross-coupled differential; inductive telemetry;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (CWCAS), 2012 IEEE 4th Colombian Workshop on

Conference_Location

Barranquilla

Print_ISBN

978-1-4673-4612-2

Type

conf

DOI

10.1109/CWCAS.2012.6404061

Filename

6404061