Design of back telemetry system on CMOS ON SEMI C5 mixed-signal technology

This paper presents design of a back telemetry system on CMOS ON - SEMI C5 mixed-signal technology. The designed system uses a different schema in order to improve the amount of information sent from the internal unit to the external unit using an alternative scheme without a load modulation strategy. The presented topology has a nontraditional architecture based on a 915 MHz voltage-controlled oscillator LC Cross-Coupled Differential. The designed system has a power consumption of 31.98mW and it represents a 6.5% of total area of 1.5 mm × 1.5 mm chip. The system was validated and simulated through Mentor Graphics IC Nanometer Electronic design automation (EDA) toolkit.