Title :
A three transistor-cell, 1024-bit, 500 NS MOS RAM
Author :
Regitz, W. ; Karp, Jann
Author_Institution :
Honey Well/Computer control Division, Framingham, MA, USA
Abstract :
An MOS semiconductor memory array has been designed for main memory usage. The array is fully decoded, with a 500-ns read and write cycle, and 345-ns access time: uses three minimum-geometry MOS transistors per cell.
Keywords :
Costs; Decoding; Integrated circuit interconnections; Inverters; MOSFETs; Magnetics; Packaging; Random access memory; Read-write memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1970.1154796
