DocumentCode
2849170
Title
3D Chip-to-Chip Stacking with Through Silicon Interconnects
Author
Lo, Wei-Chung ; Chang, Shu-Ming ; Chen, Yu-Hua ; Ko, Jeng-Dar ; Kuo, Tzu-Ying ; Chang, Hsiang-Hung ; Shih, Ying-Ching
Author_Institution
Adv. Packaging Technol. Div., Hsinchu
fYear
2007
fDate
23-25 April 2007
Firstpage
1
Lastpage
2
Abstract
The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on LTSI confirm that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.
Keywords
chip scale packaging; integrated circuit interconnections; integrated circuit reliability; silicon; 3D SiP module; 3D chip-to-chip stacking technology; 3D chip-to-wafer stacking; 3D stacking packaging; 3D wafer-to-wafer stacking; LTSI; Si; laser-drilled through silicon interconnect; thermal effect; Copper; Costs; Dielectric materials; Drilling; Filling; Packaging; Paper technology; Silicon; Stacking; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
1-4244-0584-X
Electronic_ISBN
1524-766X
Type
conf
DOI
10.1109/VTSA.2007.378925
Filename
4239493
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