Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications

Author

Chiang, W.T. ; Pan, J.W. ; Liu, P.W. ; Tsai, C.H. ; Tsai, C.T. ; Ma, G.H.

Author_Institution

United Microelectron. Corp. (UMC), Hsinchu

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

2

Abstract

High performance SiGe channel CMOS on (100) and (110) Si surfaces with process-induced strained-Si technologies was fabricated and compared to Si channel devices. The mechanism of stress-induced performance enhancements in SiGe channel devices on both (100) and (110) surfaces was systematically investigated. Device-level piezoresistance coefficients for Si and SiGe channels were extracted from CMOS transistors with external mechanical stress applied. The results were consistent with device drive current enhancement induced by the CESL strained scheme.

Keywords

CMOS analogue integrated circuits; Ge-Si alloys; MOSFET; integrated circuit testing; piezoresistance; silicon; stress effects; CESL strained scheme; CMOS transistor; Si; SiGe; drive current enhancement; mechanical stress; piezoresistance coefficient; process-induced strained-Si technology; CMOS technology; Capacitive sensors; Compressive stress; Germanium silicon alloys; MOSFETs; Microelectronics; Piezoresistance; Piezoresistive devices; Silicon germanium; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378930

Filename

4239498