A design technique for high Q-factor SI filters

Author

Shlemin, D.L.

Author_Institution

Siberian State Univ. of Telecommun. & Inf. Sci., Novosibirsk, Russia

fYear

1998

fDate

1998

Firstpage

142

Lastpage

152

Abstract

A problem of SI realisation of a high quality (Q) factor biquadratic filter is considered with emphasis on the signal-dependent clock feedthrough (SDCF) influence upon sensitivities of filter design parameters. The CMOS digital gate array-based implementation of medium Q-factor biquadratic filter resulted in a high random deviation of Q-factor value. An explanation of the phenomenon considered has been found by means of biquadratic filter model analysis taking into account the SDCF effect. It has been shown that a significant reduction of Q-factor sensitivities is possible to achieve through the use of an optimised DC-transfer-function voltage-to-current converter (VCC). A new S²I memory cell utilising this VCC has been proposed and its advantage compared to the current state-of-the-art S²I memory cell demonstrated

Keywords

CMOS memory circuits; SPICE; biquadratic filters; sampled data filters; switched current circuits; switched filters; CMOS digital gate array-based implementation; S²I memory cell; SPICE; biquadratic filter; design parameter sensitivity; design technique; filter model analysis; high Q-factor; impulse response; medium Q-factor filter; optimised DC-transfer-function; signal-dependent clock feedthrough; switched current filters; voltage-to-current converter; Analog-digital conversion; CMOS process; Capacitance; Circuits; Digital filters; Logic arrays; Operational amplifiers; Q factor; Transfer functions; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Instrument Engineering Proceedings, 1998. APEIE-98. Volume 1. 4th International Conference on Actual Problems of

Conference_Location

Novosibirsk

Print_ISBN

0-7803-4938-5

Type

conf

DOI

10.1109/APEIE.1998.768932

Filename

768932