• DocumentCode
    2849649
  • Title

    BADCO: Behavioral Application-Dependent Superscalar Core model

  • Author

    Velasquez, Ricardo A. ; Michaud, Pierre ; Seznec, Andre

  • Author_Institution
    IRISA, INRIA, Rennes, France
  • fYear
    2012
  • fDate
    16-19 July 2012
  • Firstpage
    58
  • Lastpage
    67
  • Abstract
    Microarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approximate microarchitecture models, which trade accuracy for simulation speed, are very useful for research and design space exploration, provided the loss of accuracy remains acceptable. Behavioral superscalar core modeling is a possible way to trade accuracy for simulation speed in situations where the focus of the study is not the core itself. In this approach, a superscalar core is viewed as a black box emitting requests to the uncore at certain times. A behavioral core model can be connected to a cycle-accurate uncore model. Behavioral core models are built from cycle-accurate simulations. Once the time to build the model is amortized, important simulation speedups can be obtained. We describe and study a new method for defining behavioral models for modern superscalar cores. The proposed Behavioral Application-Dependent Superscalar Core model, BADCO, predicts the execution time of a thread running on a superscalar core with an error less than 10% in most cases. We show that BADCO is qualitatively accurate, being able to predict how performance changes when we change the uncore. The simulation speedups we obtained are typically between one and two orders of magnitude.
  • Keywords
    microprocessor chips; multiprocessing systems; BADCO model; behavioral application-dependent superscalar core model; cycle-accurate simulation; cycle-accurate uncore model; design space exploration; execution time; microarchitecture development; microarchitecture research; processor development; simulation accuracy; simulation speed; Accuracy; Adaptation models; Buildings; Load modeling; Mathematical model; Microarchitecture; Multicore processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Computer Systems (SAMOS), 2012 International Conference on
  • Conference_Location
    Samos
  • Print_ISBN
    978-1-4673-2295-9
  • Electronic_ISBN
    978-1-4673-2296-6
  • Type

    conf

  • DOI
    10.1109/SAMOS.2012.6404158
  • Filename
    6404158