Author :
Sukegawa, K. ; Okuno, M. ; Ochimizu, H. ; Yamaji, M. ; Fukuda, M. ; Sanbonsugi, Y. ; Kudo, H. ; Yoshida, E. ; Mizushima, Y. ; Arita, T. ; Yamamoto, T. ; Shimoda, Y. ; Osawa, M. ; Yao, T. ; Futatsuya, H. ; Terahara, M. ; Tajima, M. ; Ogura, J. ; Oryoji, M.
Abstract :
A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasized that this technology is cost-effective.
Keywords :
CMOS integrated circuits; SRAM chips; copper; integrated circuit interconnections; semiconductor junctions; LSTP CMOS technology; SRAM cell; copper interconnects; cost-effective technology; lithography; low-leak transistors fabrication; size 45 nm; CMOS technology; Costs; Design optimization; Dielectrics; Energy consumption; Leakage current; Lithography; MOSFET circuits; Random access memory; Transistors;
