A framework for efficient cache resizing

We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the running applications. Our framework enables smooth scaling (i.e., resizing) of the on-chip caches targeting both performance and power efficiency. In contrast to previous approaches, the resizing decisions in our framework are not tainted by transient events (e.g., misses) that are due to downsizing avoiding at the same time swinging the cache size due to trial-and-error resizing decisions. This minimizes both execution time penalty induced by resizing as well as the effective cache size. Furthermore, an inherent property of our approach is that the actual invalidation of the cache blocks and the corresponding write-backs of the dirty blocks are asynchronous to resizing decisions, ensuring a smooth transition from one size to another. This makes it possible to apply our framework even on write-back caches. The proposed mechanism is simple to implement requiring minimal additional hardware. Using cycle-accurate simulations, we evaluate our proposal against previously proposed techniques. In all cases, our experimental results show significant benefits in both power and performance.