Title :
A novel low-power high-date-rate BPSK demodulator
Author :
Wang, B. ; Liu, H.H. ; Zhao, M.J. ; Li, B.
Author_Institution :
Sch. of Electron. & Inf. Eng., South China Univ. of Technol., Guangzhou, China
Abstract :
A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design is fully digital and based on trigger receiving. The demodulator can be applied in wireless communications, biological implants, portable facilities because of its low complexity, low power and high data rate. The prototype chip is fabricated in a 0.35-μm CMOS process and the area of the designed circuits is about 0.5 mm2. Measurement results reveal that the designed demodulator consumes only 319 μw power for the data rate of 10.7MHz 1M bit/s, results also show that it can work well to the high data rate of 100MHz 10M bit/s, which is the highest performance of the BPSK demodulator.
Keywords :
CMOS integrated circuits; demodulators; low-power electronics; phase shift keying; BPSK demodulator architecture; CMOS process; binary phase-shift keying; biological implants; high data rate; low complexity; low power; low-power high-date-rate BPSK demodulator; portable facilities; prototype chip; trigger receiving; wireless communications; Binary phase shift keying; Biology; Clocks; Demodulation; Frequency measurement; Implants; Wireless communication; Binary phase-shift keying (BPSK); demodulator; wireless implant;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location :
Tianjin
Print_ISBN :
978-1-4577-1998-1
Electronic_ISBN :
Pending
DOI :
10.1109/EDSSC.2011.6117625
