DocumentCode
2849844
Title
A pragmatic approach to systolic design
Author
Manohar, Swaminathan ; Baudet, Gerard
Author_Institution
Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
fYear
1988
fDate
25-27 May 1988
Firstpage
463
Lastpage
472
Abstract
Limitations of current systolic designs are pointed out, and constraints are imposed to make systolic solutions practical. Matrix multiplication is used as an illustration, and a simple but very-high-performance systolic architecture, the Superprocessor for Matrix Problems (S-MP), that satisfies these constraints is presented. Implementation alternatives for the linear systolic array for matrix-vector multiplication, which forms the core of S-MP are described
Keywords
cellular arrays; digital arithmetic; matrix algebra; parallel architectures; Superprocessor for Matrix Problems; linear systolic array; matrix-vector multiplication; systolic architecture; systolic design; Bandwidth; Computer architecture; Computer science; Costs; Hardware; Image processing; Matrix decomposition; Signal processing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18083
Filename
18083
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