DocumentCode
2850484
Title
The ASP, a fault tolerant VLSI/ULSI/WSI associative string processor for cost-effective systolic processing
Author
Lea, R.M.
Author_Institution
Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
fYear
1988
fDate
25-27 May 1988
Firstpage
515
Lastpage
524
Abstract
The author discusses the Associative String Processor (ASP), a homogeneous, reconfigurable, and programmable parallel processing computational architecture that provides the base technology for the development of high-performance, fault-tolerant computer add-on processors to be applied to a wide range of information processing tasks. He presents the architectural principles and VLSI/ULSI/WSI implementation of the ASP and indicates its cost-performance potential
Keywords
VLSI; fault tolerant computing; parallel architectures; cost-effective systolic processing; fault tolerant VLSI/ULSI/WSI associative string processor; fault-tolerant computer add-on processors; programmable parallel processing computational architecture; Application specific processors; Communication networks; Communication system control; Computer buffers; Concurrent computing; Fault tolerance; High performance computing; Parallel processing; Ultra large scale integration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18088
Filename
18088
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