A high speed wide band low phase noise multi-mode frequency divider for DRM/DAB/AM/FM frequency synthesizer

Author

Xuemei, Lei ; Zhigong, Wang ; Keping, Wang

Author_Institution

Coll. of Electron. Inf. Eng., Inner Mongolia Univ., Hohhot, China

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

The implementation of a high-speed wide band low phase noise multi-mode frequency divider (MMFD) for a DRM/DAB frequency synthesizer is described. According to the characteristics of each part, novel SCL and CMOS static flip-flop DFF are applied. Realized in a 0.18-μm RF CMOS technology, the core area of the MMFD is 745 μm×705 μm, including buffer and pads. Post simulated results show that its operation frequency ranging is from 2.2GHz to 3.1 GHz, and phase noise of the MMFD is -134dBc/Hz at 10 kHz offset. The maximum core power consumption is 24.6 mA at a 1.8V power supply.

Keywords

CMOS integrated circuits; UHF integrated circuits; flip-flops; frequency dividers; frequency synthesizers; microwave integrated circuits; phase noise; CMOS static flip-flop DFF; DRM-DAB-AM-FM frequency synthesizer; RF CMOS technology; SCL static flip-flop DFF; digital audio broadcasting; digital radio mondiale; frequency 2.2 GHz to 3.1 GHz; high speed wide band low phase noise multimode frequency divider; high-speed wide band low phase noise frequency MMFD; power 24.6 mW; size 0.18 mum; voltage 1.8 V; CMOS integrated circuits; Educational institutions; Frequency conversion; Frequency modulation; Frequency synthesizers; Phase noise; Radio frequency; DRM/DAB/AM/FM frequency synthesizer; Low phase noise; Wide band; high speed; multi-mode frequency divider (MMFD);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117667

Filename

6117667