Title :
The verification of network processor Fast Bus Interface using SystemVerilog
Author :
Pei-Jun, Ma ; Wen-Bo, Ma ; Kang, Li ; Jiang-Yi, Shi ; Yong, Jiang
Author_Institution :
Key Lab. of Wide Band-Gap Semicond. Mater. & Devices, Xidian Univ., Xi´´an, China
Abstract :
According to the background of network processor XDNP, this article describes a design of Fast Bus Interface(FBI) verification platform based on VMM architecture. All of the components and codes in the verification platform are achieved by SystemVerilog and assertions are also used in the process of verification. Through resonable usage of SVA it bacomes much easier to check out errors occuring in the executive process of FBI quickly and exactly. And then, the valuable functional verification results are obtained.
Keywords :
formal verification; hardware description languages; system buses; SystemVerilog; VMM architecture; fast bus interface verification platform; network processor XDNP; network processor fast bus interface; valuable functional verification; Educational institutions; Generators; Microelectronics; Monitoring; Presses; SDRAM; System-on-a-chip; FBI; Fast Bus Interface; SystemVerilog; VMM; assertion; verification;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location :
Tianjin
Print_ISBN :
978-1-4577-1998-1
Electronic_ISBN :
Pending
DOI :
10.1109/EDSSC.2011.6117669
