DocumentCode
285076
Title
Parallely cascaded heterogeneous perceptron applied to base-4 digital computations
Author
Hu, Chia-lun J.
Author_Institution
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Volume
2
fYear
1992
fDate
7-11 Jun 1992
Firstpage
895
Abstract
A heterogeneous perceptron circuit cascaded in a parallel manner is proposed here to implement the base-4 digital multiplication process. The design follows the universal mapping characteristic of a parallely cascaded heterogeneous perceptron system cascaded in a parallel fashion. This heterogeneous system allows one to use the base-4 digital computation much more efficiently than any conventional binary neural-network system. The origin of this heterogeneous system and a numerical design of the system are reported in detail
Keywords
digital arithmetic; many-valued logics; multiplying circuits; base-4 digital computation; base-4 digital multiplication process; heterogeneous perceptron circuit; parallely cascaded heterogeneous perceptron system; Circuits; Computer applications; Computer networks; Concurrent computing; Digital arithmetic; Digital systems; Hardware; Neural networks; Process design; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1992. IJCNN., International Joint Conference on
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-0559-0
Type
conf
DOI
10.1109/IJCNN.1992.226874
Filename
226874
Link To Document