Title :
A VLSI neural network for morphology classification
Author :
Leong, Philip H W ; Jabri, Marwan A.
Author_Institution :
Dept. of Electr. Eng., Sydney Univ., NSW, Australia
Abstract :
An architecture for a low-power analog VLSI implementation of a three-layer perceptron is presented. The chip is designed specifically for the classification of signals obtained from the internal surface of the heart. The neural network is composed of synapses which are implemented as multiplying digital to analog converters, and neurons which are high resistance off-chip resistors. A test chip with a (3,3,1) neural network and bucket brigade has been fabricated, and results from this test chip are presented
Keywords :
VLSI; analogue computer circuits; neural chips; VLSI neural network; bucket brigade; morphology classification; test chip; three-layer perceptron; Digital-analog conversion; Heart; Multilayer perceptrons; Neural networks; Neurons; Signal design; Surface morphology; Surface resistance; Testing; Very large scale integration;
Conference_Titel :
Neural Networks, 1992. IJCNN., International Joint Conference on
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-0559-0
DOI :
10.1109/IJCNN.1992.226909
