Title :
A new approach to sea-of-gates global routing
Author :
Parng, T.-M. ; Tsay, R.-S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The authors integrate the concepts and techniques of two existing complementary approaches, namely, the rerouting approach and the top-down hierarchical approach based on linear assignment. This combines and enhances the advantages of the two approaches and results in a fast and high-quality router which can handle large sea-of-gates designs. In addition, it solves the problems of routing interdependence and routing resource estimation which heretofore have not been well addressed yet. The method has been implemented and successfully tested on three real gate-arrays chips: Primary 1, Primary 2, and a channelless industrial example with 100 K gates.<>
Keywords :
circuit layout CAD; logic CAD; logic arrays; Primary 1; Primary 2; channelless industrial example; gate-arrays chips; linear assignment; rerouting approach; routing interdependence; routing resource estimation; sea-of-gates global routing; top-down hierarchical approach; Costs; Councils; Laboratories; Read only memory; Routing; Testing;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76903
