Title :
Design and FPGA implementation of systolic FIR filters using the Fermat number ALU
Author :
Safiri, H. ; Ahmadi, M. ; Jullien, G.A. ; Dimitrov, V.S.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
Abstract :
This paper addresses the implementation of systolic FIR filters over finite polynomial rings, using FPGAs. The use of residue computations is a potentially beneficial solution to the design of high throughput DSP systems on FPGAs. This paper describes a new architecture for a multiply/accumulate architecture over the fields GF(17) and GF(257). The computational unit containing both GF(17) and GF(257) elements is referred to as the Fermat ALU. The ALU is pipelined completely by using an abundant number of flip flops available in Xilinx FPGA parts. The simulation results show a relatively high throughput for the filter designed using this methodology
Keywords :
FIR filters; Galois fields; digital filters; digital signal processing chips; field programmable gate arrays; pipeline arithmetic; polynomials; systolic arrays; Fermat number ALU; Galois fields; Xilinx FPGA; architecture; computational unit; finite polynomial rings; flip flops; high throughput DSP systems; multiply/accumulate architecture; pipelined ALU; residue computations; simulation results; systolic FIR filters; Computational modeling; Computer architecture; Design methodology; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Polynomials; Read only memory; Throughput; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7646-9
DOI :
10.1109/ACSSC.1996.599104
