A Novel Method of Test Generation for Asynchronous Circuits

Design of asynchronous circuits involves primitive structures which have local feedback loops like C-elements. Due to the presence of number of such primitive elements, the loops in asynchronous circuits are high. Increased number of loops in these cyclic asynchronous circuits makes the conventional synchronous CAD tools to fail as they are capable of only handling acyclic circuits. This makes the generation of test patterns for asynchronous circuits a hard task. This paper focuses on this problem and deals with the test generation process involving the conversion of cyclic asynchronous structures to equivalent acyclic structures before generating test and thereby improving the fault coverage. Thus, enabling the test generation for these circuits and increasing the fault coverage.