A hardware efficient implementation of chroma interpolator for H.264 encoders

Author

Wang, Teng ; Zhao, Lei ; Hu, Ziyi ; Xie, Zheng ; Wang, Xin An

Author_Institution

Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.

Keywords

CMOS integrated circuits; field programmable gate arrays; high definition television; video codecs; CMOS technology; H.264 encoders; HDTV; SMIC; Xilinx Virtexθ FPGA; chroma interpolation; chroma interpolator; frequency 200 MHz; frequency 245 MHz; hardware efficient implementation; optimized decomposition scheme; Adders; Field programmable gate arrays; HDTV; Hardware; Interpolation; Motion estimation; Video coding; Arithmetic Decomposation; Chroma Interpolator; H.264; Hardware Resue;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117699

Filename

6117699