DocumentCode :
2851171
Title :
Study on Universal Bus Interface Based on Sequence Configuration
Author :
Zhang, Duoli ; Du, Gaoming ; Song, Yukun ; Jia, Jinghua
Author_Institution :
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
fYear :
2009
fDate :
11-13 Dec. 2009
Firstpage :
1
Lastpage :
4
Abstract :
Universal bus interface is very helpful for improving the popularity of the device or equipment on both SoC integration and board level computing system design. Because of the diversity of bus interface accessing protocol, universality is usually unable to be achieved in a common interface design. Through introducing the concept of sequence configuration, a method of designing universal bus interface was proposed in this paper. The concept of the bus accessing sequence configuration was analyzed, the specification definition of the universal interface was elaborated and then the architecture was discussed. As a case study, a universal bus writer was implemented and embedded in a FPGA based computing system in real use. Application status shows that the universal bus interface designed through this method can be configured into various kinds of bus interface access timing with distinct cost advantage.
Keywords :
peripheral interfaces; system-on-chip; FPGA based computing system; SoC integration; board level computing system design; bus accessing sequence configuration; bus interface accessing protocol; universal bus interface; universal bus writer; Access protocols; Circuits; Computer architecture; Computer interfaces; Costs; Design methodology; Embedded computing; Field programmable gate arrays; Standardization; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Intelligence and Software Engineering, 2009. CiSE 2009. International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-4507-3
Electronic_ISBN :
978-1-4244-4507-3
Type :
conf
DOI :
10.1109/CISE.2009.5365395
Filename :
5365395
Link To Document :
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