Hardware implementation of trained networks

It is shown that by considering network nodal functions as polynomials and introducing alternative functions, a network can be collapsed to an equation for each output and thus be implemented in analog hardware. Two examples of collapsing are given, together with the implementation of a network approximation to a Boolean function. These examples illustrate advantages over conventional digital implementation techniques. At present the maximum switching speed for TTL or CMOS technology is on the order of tens of megahertz. The analog circuits described have switching speeds limited only by the bandwidth of the differential amplifiers used to build the multiplier circuits. Multipliers with switching speeds in excess of 500 MHz are available. Thus this approach leads to a technique for providing very high switching-speed digital circuits